A fragmentary portion of a multi-stage integrated circuit 10 is illustrated in FIG. 1 with an input stage 12 and an output stage 14. The input stage 12 is coupled to an input ground line 15 providing a relatively quiet ground (QG) and an input supply line 16 providing a relatively quiet V.sub.cc supply (QV). The input stage 12 includes input 17 and output 18 for data signals of high and low potential and may be coupled to other internal stages or to output stage 14.
The output stage 14 incorporates an input V.sub.in for receiving signals of high and low potential from input stage 12 or other internal stage and an output V.sub.out for delivering data signals. The output stage is coupled to an output ground line 20 which forms a relatively noisy power ground or output ground (PG) and an output supply line 22 which forms a relatively noisy power V.sub.cc supply or output V.sub.cc supply (PV).
The input quiet ground line QG and output ground line PG are relatively isolated by respectively coupling to the split lead fingers 25 and 26 of a lead frame split lead 24. The input and output ground lines 15, 20 therefore each incorporate the separate lead inductance associated with the respective split lead fingers 25, 26. They are relatively isolated for coupling to a common external ground through the relatively low common inductance coupling of the common lead portion 28 of the lead frame split lead 24. The common external ground of 0 volts (Ov) is designated GND. Such a split lead frame lead is illustrated in FIG 1A with its equivalent circuit inductances shown in FIG. 1.
The input and output supply lines 16, 22 are relatively isolated by coupling to the split lead fingers 30, 32 respectively of lead frame power supply split lead 34. The separate supply lead inductance associated with the respective split lead fingers 30, 32 is shown if FIG. 1. The input and output supply lines 16, 22 are coupled to a common external V.sub.cc supply, typically 5 volts, designated V.sub.cc through the relatively low common inductance coupling associated with the common split lead portion 36.
Such lead frame split leads 24, 34 for relative isolation of input and output ground rails and supply rails are further described for example in copending U.S. patent application Ser. No. 243,195 for DYNAMIC GROUND REFERENCE CHANGER FOR MULTIPLE STAGE INTEGRATED CIRCUITS, filed Sept. 8, 1988 an FWC Continuation of U.S. patent application Ser. No. 880,407 for REDUCTION IN POWER RAIL PERTURBATION filed June 30, 1986, abandoned; the Natsui Japan Patent Document 57-164548 dated Oct. 9, 1982; and the Watanabe European Patent Application 86901518.0 filed in the EPO Feb. 28, 1986, corresponding to International Application No. PCT/JP86/00106 published Sept. 12, 1986 as International Publication No. W086/05322.
As shown in FIG. 1, relative isolation of the input and output ground rails 15, 20 and the input and output supply rails 16, 22 through a single ground lead 28 and a single supply lead 36 is permitted by a split lead configuration. Alternatively, chips and chip packages are now being provided with multiple separate ground leads and supply leads for better separation. In that event, the input and output ground rails 15, 20 can be routed to external ground through entirely separate ground leads and pins. Input and output supply rails 16, 22 can be coupled to external power supply V.sub.cc through entirely separate supply leads and pins. In these new chip and pin designs, multiple power leads and pins and multiple ground leads and pins are being provided for the purposes of separation only.
As used in this discussion of background, and subsequently in the specification and claims, the phrases "power rails" and "power leads" are used generically to include both ground rails and ground leads on the one hand and supply rails and supply leads on the other hand. Thus, the relatively quiet power rails include the input quiet ground rail QG and the input quiet supply rail QV. The relatively noisy power rails include the output ground rail PG and the output supply rail PV. Generally the words "rail" and "lead" may be used synonymously, implying a conductor or line on the chip with coupling to external ground or supply.
In the case of CMOS integrated circuits as illustrated in FIG. 2, the output stage 14 includes a pulldown transistor element, in this case NMOS transistor N2 for sinking current from the output V.sub.out to output ground PG, and an output pullup transistor element, in this case PMOS transistor P2 coupled between the output V.sub.cc supply PV and the output V.sub.out for sourcing current from high potential to the output. The output stage 14 incorporates three current amplification stages. In this example two amplification stages are provided by transistor pairs P1, N1 and PIA, NIA preceding the pullup and pulldown transistor elements P2, N2.
In the case of bipolar integrated circuits, the output stage 14 as illustrated in FIG. 3 typically incorporates a bipolar output device with pulldown transistor element Q2, pullup Darlington transistor elements Q3, Q4, phase splitter transistor element Q1, input diode D1 and squaring network including transistor Q5 at the base of the pulldown transistor Q2.
Occurrence of ground bounce and undershoot in prior art multistage integrated circuits of the type shown in FIGS. 1, 2 and 3 is illustrated with reference to FIGS. 4 and 5. Considering in detail the equivalent circuit at the pulldown transistor element N2 of FIG. 2, pulldown transistor N2 sinks current from the output V.sub.out through the separate output ground lead inductance associated with split lead finger 26 and common lead inductance associated with the common split lead portion 28 to the external ground GND. The split lead construction minimizes the common lead inductance relatively isolating the quiet ground QG and its separate lead inductance associated with split lead finger 25. The output capacitance C.sub.out coupling to external ground GND adds a further capacitive reactance in the output ground circuit and completes a parasitic tank circuit including the output capacitance C.sub.out and output ground lead inductances L.sub.pg and L.sub.c.
Referring to FIG. 2, upon transition from high to low potential at the output, pulldown transistor N2 turns on. The surge or acceleration of charge develops a voltage across the inductances L.sub.pg and L.sub.c equal to L di/dt (where L=L.sub.pg +L.sub.c) resulting in ground rise or ground bounce in the output ground PG as shown in the first positive peak in the output ground PG voltage illustrated in the graph of FIG. 4. The duration of occurrence of this ground rise or ground bounce is in the order of 2 to 3 nanoseconds (ns). Because of the ground rise in the output ground PG which may typically be in the order of 2 to 2.5 volts above ground 0 volts, the falling potential at the output momentarily pauses at a level determined by the ground rise in the output ground. A smaller pulse (not shown) of for example 1 volt appears on the relatively quiet ground QG, a result of the reduced common inductance L.sub.c.
Occurrence of ground bounce may be analyzed according to the invention as follows. The total amount of charge in the load capacitance or output capacitance C.sub.out must be "dumped" or "drained" to ground through the output transistor N2. Some of the parasitic energy 1/2 v.sup.2 C.sub.out represented by this stored charge (where v=q/C.sub.out, v being the volts across the output capacitance and q the stored charge) may be dissipated in the power dissipation of the output transistor N2. The remainder energy in excess of the power dissipation in the output transistor is stored in the ground lead inductance as remainder parasitic energy 1/2 i.sup.2 L. The voltage drop during current buildup across the parasitic inductance L=L.sub.pg +L.sub.c appears as ground bounce. The magnitude of the ground bounce is proportional to the rate of change of current di/dt through the parasitic inductance which is in turn proportional to the acceleration of charge d.sup.2 q/dt.sup.2 and the acceleration of voltage d.sup.2 v/dt.sup.2 across the output capacitance C.sub.out.
Referring to FIG. 2, deceleration of the initial surge of charge through pulldown transistor N2 causes a voltage drop across the ground lead inductance of opposite polarity equal to -L di/dt resulting in a ground voltage undershoot of opposite polarity from the ground bounce. Ground undershoot may typically be as great as for example -2 volts as illustrated in the negative peak in the graph of output ground voltage PG in FIG. 4. The output capacitance C.sub.out in combination with the inductance L=L.sub.pg +L.sub.c in the power ground circuit constitutes a parasitic tank circuit which stores inertial energy in the output ground lead inductance L.sub.pg and common inductance L.sub.c. Subsequent ringing in the circuit results in further bounce and undershoot until the ground lead inductance energy is dissipated in the output transistor and related output circuit components.
Similar noise problems appear on the power supply side and supply leads of the output stage. As illustrated in FIG. 2, upon transition from low to high potential at the output, pullup transistor P2 becomes conducting with a surge or acceleration of charge from external power supply V.sub.cc to the output through the common inductance L.sub.c of the common portion 36 of supply split lead 34 and the separate lead inductance L.sub.pv of split lead finger 32. The inductive impedance and resulting voltage across this inductance equal to L di/dt causes transient droop of voltage in the output supply line PV at for example 2.5 volts, substantially below the V.sub.cc voltage of 5 volts. This so called V.sub.cc droop is illustrated in the first negative peak of the output supply voltage PV at 2.5 volts shown in the graph of FIG. 5. The voltage rise at the output V.sub.out is correspondingly delayed. A smaller droop pulse (not shown), for example 1 volt below the V.sub.cc level of 5 volts, appears on the quiet supply line QV as a result of the common inductance coupling L.sub.c.
Deceleration of the initial surge of charge through pullup transistor P2 results in a following supply voltage overshoot of opposite polarity from the PV droop as shown in the positive peak of the graph of the supply voltage PV illustrated in FIG. 5. Subsequent droop and overshoot ringing persists until the inertial energy of the supply lead inductance is dissipated in the output pullup transistor and related output circuit components. PV overshoot may typically overshoot, for example, two volts above the V.sub.cc 5 volt level with corresponding effects at the output. Smaller droop and overshoot pulses (not shown) appear on the quiet supply QV.
Occurrence of V.sub.cc droop and overshoot may be analyzed according to the invention in the same manner as ground bounce and undershoot set forth above. V.sub.cc droop and overshoot, however, are effectively a "mirror image" of the ground bounce and undershoot. Both phenomena produce transient voltages and transient noise as a result of parasitic tank circuit energy associated with output capacitance and supply or ground lead inductance in the output stage. As set forth herein the phrases "parasitic tank circuit" and "paraitic tank circuit energy" are intended to refer to these comparable equivalent circuit structures and to the "mirror image" transient noise energy that occurs on both the supply and ground sides of the output stage.
The disruptive effects of this noise on the output ground PG and output supply PV lines includes pulsing of noise on the internal relatively quiet input ground QG and supply QV lines; radio frequency radiation interference (RFI) and electromagnetic induction interference (EMI) noise which may interfere with the host system; and local threshold shifts in the reference voltages for high and low potential data signals causing false data signals. Ground noise also adversely affects separate low or quiet outputs on a common bus. For example a low output on an octal buffer experiences a rise with ground bounce, possibly causing a false high signal. These problems associated with ground and supply noise have increased in more recent integrated circuits which switch higher currents at higher speeds.
One approach to reducing output ground noise and supply noise in integrated circuits prior to the development of split leads and prior to the recent use of multiple separate ground leads and pins and multiple separate supply lead and pins was to minimize lead inductance by the use of wider lead frame ground leads and supply leads and the use of ground planes as described for example in U.S. Pat. No. 4,680,613. With the advent of split leads, and the more recent use of separate ground leads and separate supply leads, the input stages may be relatively isolated from the noisy ground leads and supply leads of the output stages. Nevertheless ground bounce and undershoot and V.sub.cc droop and overshoot remain in the output stages particularly in the latest IC product generations with high drive and fast switching. Past methods to deal with the problem of noise in the output ground and supply lines are based on slowing the inherent switching speed of the output circuit. This however entails reducing the speed over the full range of production spreads and packaging types, slowing down the slowest circuits by a substantial multiple.
A different approach is taken in U.S. Pat. application Ser. No. 243,195 for DYNAMIC GROUND REFERENCE CHANGER FOR MULTIPLE STAGE INTEGRATED CIRCUITS filed Sept. 8, 1988. Output components on the quiet ground may be switched to the output ground following transition from high to low potential at the output. These components then follow changes in the reference voltages and maintain desired threshold differences during ground bounce and ground undershoot.